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ADI AD5065BRUZ STOCK

The AD5065BRUZ is a high‑accuracy, dual 16‑bit buffered voltage‑output nanoDAC® from Analog Devices. It operates from a single 4.5 V to 5.5 V supply and provides ±1 LSB INL relative accuracy with individual reference pins for each DAC, enabling independent output ranges. The device features a versatile 3‑wire Schmitt trigger serial interface compatible with SPI, QSPI, MICROWIRE, and DSP standards, supporting clock rates up to 50 MHz. An on‑chip reference buffer and power‑on reset circuit (user‑selectable to zero scale or midscale) ensure predictable start‑up behavior. The AD5065 includes multiple power‑down modes that reduce current consumption to typically 400 nA at 5 V, with software‑selectable output loads. Additional functionality includes a hardware LDAC pin for simultaneous DAC updates (with software override), an asynchronous CLR pin that clears outputs to a programmable code (0 V, midscale, or full scale), and a hardware power‑down lockout (PDL) pin to prevent unintentional pow

GENERAL DESCRIPTION:

The AD5025/AD5045/AD5065 are low power, dual 12-/14-/16-bitbuffered voltage output nanoDAC® DACs offering relative accuracyspecifications of ±1 LSB INL with individual reference pins, andcan operate from a single 4.5 V to 5.5 V supply. The AD5025/AD5045/AD5065 also offer a differential accuracy specification of±1 LSB. The parts use a versatile 3-wire, low power Schmitttrigger serial interface that operates at clock rates up to 50 MHzand is compatible with standard SPI®, QSPI™, MICROWIRE™,and DSP interface standards. The reference for the AD5025/AD5045/AD5065 are supplied from an external pin and a refer-ence buffer is provided on chip. The AD5025/AD5045/AD5065incorporate a power-on reset circuit that ensures the DAC outputpowers up zero scale or midscale and remains there until a validwrite takes place to the device. The AD5025/AD5045/AD5065contain a power-down feature that reduces the current consumption of the device to typically 400 nA at 5 V and provides softwareselectable output loads while in power-down mode. The parts areput into power-down mode over the serial interface. Total unadjusted error for the parts is <2.5 mV. The parts exhibit very lowglitch on power-up. The outputs of all DACs can be updatedsimultaneously using the LDAC function, with the addedfunctionality of user-selectable DAC channels to simultaneouslyupdate. There is also an asynchronous CLR that clears all DACsto a software-selectable code—0 V, midscale, or full scale. Theparts also feature a power-down lockout pin, PDL, which can beused to prevent the DAC from entering power-down under anycircumstances over the serial interface. 

FEATURES:

Low power dual 12-/14-/16-bit DAC, ±1 LSB INL

Individual voltage reference pins

Rail-to-rail operation

4.5 V to 5.5 V power supply

Power-on reset to zero scale or midscale

Power down to 400 nA @ 5 V

3 power-down functions

Per channel power-down

Low glitch upon power-up

Hardware power-down lockout capability

Hardware LDAC with software LDAC override function

CLR function to programmable code

SDO daisy-chaining option

14-lead TSSOP

APPLICATIONS:

Process controls

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators


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