General Description:

Xilinx® 7 series FPGAs comprise three new FPGA families that address the complete range of system requirements, ranging from low cost, small formfactor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the mostdemanding high-performance applications. The 7 series FPGAs include:

• Artix®-7 Family: Optimized for lowest cost and power with smallform-factor packaging for the highest volume applications.

• Kintex®-7 Family: Optimized for best price-performance with a 2Ximprovement compared to previous generation, enabling a new classof FPGAs.

• Virtex®-7 Family: Optimized for highest system performance andcapacity with a 2X improvement in system performance. Highestcapability devices enabled by stacked silicon interconnect (SSI)technology.

Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable anunparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% lesspower than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs. 

Summary of 7 Series FPGA Features:

• Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.

• 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.

• High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.

• High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to maximum rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.

• A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.

• DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high performance filtering, including optimized symmetric coefficient filtering.

• Powerful clock management tiles (CMT), combining phase-lockedloop (PLL) and mixed-mode clock manager (MMCM) blocks for highprecision and low jitter.

• Integrated block for PCI Express® (PCIe), for up to x8 Gen3Endpoint and Root Port designs.

• Wide variety of configuration options, including support forcommodity memories, 256-bit AES encryption with HMAC/SHA-256authentication, and built-in SEU detection and correction.

• Low-cost, wire-bond, lidless flip-chip, and high signal integrity flipchip packaging offering easy migration between family members inthe same package. All packages available in Pb-free and selectedpackages in Pb option.

• Designed for high performance and lowest power with 28 nm,HKMG, HPL process, 1.0V core voltage process technology and0.9V core voltage option for even lower power.