Features:

◆ Power supply: VDD = VDDQ=1.35V (1.283 - 1.45V)

◆ Backward compatible to VDD = VDDQ = 1.5V ±0.075V

– Supports DDR3L devices to be backward compatible in 1.5V application

◆ Package: 78 balls FBGA (x8)

◆ 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for1600Mb/sec/pin, 933MHz fCK for 1866Mb/sec/pin and 1067 MHz fCK for 2133Mb/sec/pin

◆ Array configuration: 8 Banks

◆ 8-bit prefetch architecture

◆ Differential clock inputs (CK, CK#)

◆ Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals

◆ Programmable CAS (READ) latency (CL)

◆ Programmable posted CAS additive latency (AL)

◆ Programmable CAS (WRITE) latency (CWL)

◆ Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])

◆ Selectable BC4 or BL8 on-the-fly (OTF)

◆ Self refresh mode

◆ Operating case temperature: 0 ℃ ≤ TCASE ≤ 95 ℃

◆ Average Refresh Period:

- 7.8 us at 0 ℃ ≤ TCASE ≤ 85 ℃

-3.9 us at 85 ℃ ≤ TCASE ≤ 95 ℃

◆ JEDEC JESD79-3E compliant

◆ RoHS compliant