Introduction:

T31ZX is a smart video application processor targeting for video devices like mobile camera, securitysurvey, video talking, video analysis and so on. This SoC introduces a kind of innovative architecturetofulfill both high performance computing and high quality image and video encoding requirementsaddressed by video devices. T31ZX provides high-speed CPU computing power, excellent image signalprocess, fluent 2592x2048 resolution video recording. The CPU (Central Processing Unit) core, equipped with 32kB instruction and 32kB data L1 cache, and128kB L2 cache, operating at 1.4GHz, and full feature MMU function performs OS related tasks. At theheart of the CPU core is XBurst® processor engine. XBurst® is an industry leading microprocessor corewhich delivers superior high performance and best-in-class low power consumption. A hardwarefloating-point unit which compatible with IEEE754 is also included. The VPU (Video Processing Unit) core is a video encoder engine designed to process video streams usingthe HEVC(ISO/IEC 23008-2 High Efficiency Video Coding) and AVC(ISO/IEC 14496-10 Advanced VideoCoding) standards. It also supports still picture encoding using the JPEG standard(ITU T.81). Togetherwith the on chip video accelerating engine and post image processing unit, T31ZX delivers high videoperformance. The maximum resolution of 2592x2048 in the format of AVC are supported in encoding. up to 40Mbit/s, 2592x2048@25fps. The ISP (Image signal processor) core supports excellent image process with the image fromrawsensors.It supports DVP,BT and MIPI interface. With the functions, such as 3A, 2D and 3D denoise, WDR/HDR,lens shading, it can supply maximum resolution 2592x2048 resolution image for view or encoding tostore or transfer. For more quickly and easily to use T31ZX, 1G bit DDR2 is integrated on chip. On-chip modules such as audio CODEC, multi-channel SAR-ADC controller and camera interface offerdesigners a economical suite of peripherals for video application. WLAN, Bluetooth and expansionoptions are supported through high-speed SPI and MMC/SD/SDIO host controllers. Other peripheralssuch as USB OTG, MAC, UART and SPI as well as general system resources provide enough computingand connectivity capability for many applications.

Features:

CPU

 XBurst®-1 core 

– XBurst® FPU instruction set supporting both single and double floating point format whichare IEEE754 compatible 

– XBurst® 9-stage pipeline micro-architecture, the operating frequency is 1.4GHz 

 MMU 

– 32-entry joint-TLB

 – 8 entry instruction TLB 

– 8 entry data TLB

 L1 Cache 

– 32kB instruction cache 

– 32kB data cache

  Hardware debug support

  16kB tight coupled memory 

 L2 Cache 

– 128kB unify cache