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micron MT29F1G08ABAEAWP-ITE Datesheet

The MT29F1G08ABAEAWP-ITE is a 1-gigabit (128MB) SLC (Single-Level Cell) NAND Flash memory device from Micron, designed for reliable, high-performance data storage in embedded and industrial applications. This device complies with the Open NAND Flash Interface (ONFI) 1.0 specification, ensuring broad compatibility with standard NAND controllers. Organized as 1024 blocks, each containing 64 pages, the device offers a page size of 2112 bytes (2048 + 64 spare bytes) in x8 configuration. It delivers fast asynchronous I/O performance with access times (tRC/tWC) of 20ns at 3.3V and 25ns at 1.8V, with typical program and erase times of 200µs and 700µs, respectively. Advanced command features include program page cache, read page cache, two-plane commands, OTP (One-Time Programmable) mode, internal data move, and block lock (1.8V only), providing flexibility for complex system designs.

Features:

• Open NAND Flash Interface (ONFI) 1.0-compliant1

• Single-level cell (SLC) technology

• Organization

– Page size x8: 2112 bytes (2048 + 64 bytes)

– Page size x16: 1056 words (1024 + 32 words)

– Block size: 64 pages (128K + 4K bytes)

– Plane size: 2 planes x 512 blocks per plane

– Device size: 1Gb: 1024 blocks

• Asynchronous I/O performance

–tRC/tWC: 20ns (3.3V), 25ns (1.8V)

• Array performance

– Read page: 25µs

– Program page: 200µs (TYP, 3.3V and 1.8V)

– Erase block: 700µs (TYP)

• Command set: ONFI NAND Flash Protocol

• Advanced command set

– Program page cache mode

– Read page cache mode

– One-time programmable (OTP) mode

– Two-plane commands

– Read unique ID

– Internal data move

– Block lock (1.8V only)

• Operation status byte provides software method fordetecting

– Operation completion

– Pass/fail condition

– Write-protect status

• Internal data move operations supported within thedevice from which data is read

• Ready/busy# (R/B#) signal provides a hardwaremethod for detecting operation completion

• WP# signal: write protect entire device

• First block (block address 00h) is valid when shipped from factory with ECC. For minimum requiredECC, see Error Management.

• Block 0 requires 1-bit ECC if PROGRAM/ERASE cycles are less than 1000

• RESET (FFh) required as first command after power-on

• Alternate method of device initialization (Nand_Init) after power up3 (contact factory)

• Quality and reliability

– Data retention: JESD47 compliant; see qualification report

– Endurance: 100,000 PROGRAM/ERASE cycles

• Operating Voltage Range

– VCC: 2.7–3.6V– VCC: 1.7–1.95V

• Operating temperature:

– Commercial (CT): –0ºC to +70ºC

– Industrial (IT): –40ºC to +85ºC

• Package– 48-pin TSOP Type 1, CPL2


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