Features:

This datasheet is for LPDDR4 and LPDDR4X unifiedproduct based on LPDDR4X information. Refer toLPDDR4 setting section LPDDR4 1.10V VDDQ at theend of this datasheet.

• Ultra-low-voltage core and I/O power supplies– VDD1 = 1.70–1.95V; 1.80V nominal– VDD2 = 1.06–1.17V; 1.10V nominal– VDDQ = 1.06–1.17V; 1.10V nominalor Low VDDQ = 0.57–0.65V; 0.60V nominal

• Frequency range– 2133–10 MHz (data rate range: 4266–20 Mb/s/pin)

• 16n prefetch DDR architecture

• 8 internal banks per channel for concurrent operation

• Single-data-rate CMD/ADR entry

• Bidirectional/differential data strobe per byte lane

• Programmable READ and WRITE latencies (RL/WL)

• Programmable and on-the-fly burst lengths (BL =16, 32)

• Directed per-bank refresh for concurrent bank operation and ease of command scheduling

• Up to 8.5 GB/s per die

• On-chip temperature sensor to control self refreshrate

• Partial-array self refresh (PASR)

• Selectable output drive strength (DS)

• Clock-stop capability

• RoHS-compliant, “green” packaging

• Programmable VSS (ODT) termination