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Home > Products > ST MICROELECTRONICS > STM32

ST STM32H743VIH6 Datesheet

The STM32H743VIH6 is a flagship high-performance microcontroller from the STM32H7 series, built around the ARM® 32-bit Cortex®-M7 core with a double-precision FPU and L1 cache (16 Kbytes each for instructions and data). Operating at frequencies up to 480 MHz, it delivers an outstanding 1027 DMIPS (2.14 DMIPS/MHz) performance, making it ideal for compute-intensive and real-time applications.This device features a massive memory architecture with up to 2 Mbytes of Flash (read-while-write support) and up to 1 Mbyte of RAM, including Tightly-Coupled Memory (TCM) for critical routines, large user SRAM, and backup SRAM.

Features:

Includes ST state-of-the-art patentedtechnologyCore

• 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of dataand 16 Kbytes of instruction cache; frequencyup to 480 MHz, MPU, 1027 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSPinstructionsMemories

• Up to 2 Mbytes of Flash memory with readwhile-write support

• Up to 1 Mbyte of RAM: 192 Kbytes of TCMRAM (inc. 64 Kbytes of ITCM RAM +128 Kbytes of DTCM RAM for time criticalroutines), Up to 864 Kbytes of user SRAM, and4 Kbytes of SRAM in Backup domain

• Dual mode Quad-SPI memory interfacerunning up to 133 MHz

• Flexible external memory controller with up to32-bit data bus: SRAM, PSRAM,SDRAM/LPSDR SDRAM, NOR/NAND Flashmemory clocked up to 100 MHz inSynchronous mode

• CRC calculation unitSecurity

• ROP, PC-ROP, active tamperGeneral-purpose input/outputs

• Up to 168 I/O ports with interrupt capabilityReset and power management

• 3 separate power domains which can beindependently clock-gated or switched off:– D1: high-performance capabilities

– D2: communication peripherals and timers– D3: reset/clock control/power management

• 1.62 to 3.6 V application supply and I/Os

• POR, PDR, PVD and BOR

• Dedicated USB power embedding a 3.3 Vinternal regulator to supply the internal PHYs

• Embedded regulator (LDO) with configurablescalable output to supply the digital circuitry

• Voltage scaling in Run and Stop mode (6configurable ranges)

• Backup regulator (~0.9 V)

• Voltage reference for analog peripheral/VREF+

• Low-power modes: Sleep, Stop, Standby andVBAT supporting battery chargingLow-power consumption

• VBAT battery operating mode with chargingcapability

• CPU and domain power state monitoring pins

• 2.95 µA in Standby mode (Backup SRAM OFF,RTC/LSE ON)Clock management

• Internal oscillators: 64 MHz HSI, 48 MHzHSI48, 4 MHz CSI, 32 kHz LSI

• External oscillators: 4-48 MHz HSE,32.768 kHz LSE

• 3× PLLs (1 for the system clock, 2 for kernelclocks) with Fractional modeInterconnect matrix

• 3 bus matrices (1 AXI and 2 AHB)

• Bridges (5× AHB2-APB, 2× AXI2-AHB)4 DMA controllers to unload the CPU

• 1× high-speed master direct memory accesscontroller (MDMA) with linked list support

• 2× dual-port DMAs with FIFO

• 1× basic DMA with request router capabilitiesUp to 35 communication peripherals

• 4× I2Cs FM+ interfaces (SMBus/PMBus)

• 4× USARTs/4x UARTs (ISO7816 interface,LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART

• 6× SPIs, 3 with muxed duplex I2S audio classaccuracy via internal audio PLL or externalclock, 1x I2S in LP domain (up to 150 MHz)

• 4x SAIs (serial audio interface)

• SPDIFRX interface

• SWPMI single-wire protocol master I/F

• MDIO Slave interface

• 2× SD/SDIO/MMC interfaces (up to 125 MHz)

• 2× CAN controllers: 2 with CAN FD, 1 withtime-triggered CAN (TT-CAN)

• 2× USB OTG interfaces (1FS, 1HS/FS) crystalless solution with LPM and BCD

• Ethernet MAC interface with DMA controller

• HDMI-CEC

• 8- to 14-bit camera interface (up to 80 MHz)11 analog peripherals

• 3× ADCs with 16-bit max. resolution (up to 36channels, up to 3.6 MSPS)

• 1× temperature sensor

• 2× 12-bit D/A converters (1 MHz)

• 2× ultra-low-power comparators

• 2× operational amplifiers (7.3 MHz bandwidth)

• 1× digital filters for sigma delta modulator(DFSDM) with 8 channels/4 filters

Graphics

• LCD-TFT controller up to XGA resolution

• Chrom-ART graphical hardware Accelerator(DMA2D) to reduce CPU load

• Hardware JPEG CodecUp to 22 timers and watchdogs

• 1× high-resolution timer (2.1 ns maxresolution)

• 2× 32-bit timers with up to 4 IC/OC/PWM orpulse counter and quadrature (incremental)encoder input (up to 240 MHz)

• 2× 16-bit advanced motor control timers (up to240 MHz)

• 10× 16-bit general-purpose timers (up to240 MHz)

• 5× 16-bit low-power timers (up to 240 MHz)

• 2× watchdogs (independent and window)

• 1× SysTick timer

• RTC with sub-second accuracy and hardwarecalendarDebug mode

• SWD & JTAG interfaces

• 4-Kbyte Embedded Trace BufferTrue random number generators (3oscillators each)96-bit unique IDAll packages are ECOPACK2 compliant


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