The system clock frequency supports up to 48MHz
The fastest machine cycle supports 1TSYS @ FSYS≤24MHz
The fastest machine cycle supports 2TSYS @ FSYS=48MHz
Program FLASH:32K×8Bit
Data FLASH:1K×8Bit
IRAM:256×8Bit
XRAM:2K×8Bit
Support BOOT function area,1K/2K/4K optiona
Program FLASH supports partition protection
HSI-Internal high-speed oscillator: 48MHz
HSE-External high-speed oscillator: 8MHz/16MHz
LSE-External low-speed oscillator: 32.768KHz
LSI-Internal low-speed oscillator: 125KHz
Up to 30 GPIOs
All support up/down resistance function
All support edge (rising edge/ falling edge/ doubleedge) interrup
Support wake-up function
7 timer interrupts
Other peripheral interrupts
WDT wake-up (watchdog timer)
Timer0/1, Timer2, Timer3/4
LSE_Timer (Support sleep wake function)
WUT (wake-up wake-up)
BRT (Serial port baud rate clock generator)
CRC16 (CRC16-CCITT)
2.1V~5.5V
-40℃~105℃
1.8V/ 2.0V/ 2.5V/ 3.5V
2.0V~4.3V 8 levels optional
Up to 30 AD external channels
Optional reference voltage(1.2V/ 2.0V/ 2.4V/ 3.0V/ VDD)
Can detect internal 1.2V reference voltage
Support hardware trigger start conversion function
Support a set of result digital comparison function
50% duty cycle, frequency can be set freely
6 channels PWM
6 mutually independent cycle counters
Support independent /complementary/ synchronous/group mode
Support edge alignment
Support complementary mode dead zone delayfunction
1 x SPI (communication rate up to 6Mb/s)
1 x I2C (communication rate up to 400Kb/s)
2 x UART (baud rate up to 1Mb/s)
UART1 can be mapped to any GPIO
Idle mode (IDLE)
Sleep mode (STOP)
Each chip has an independent ID number
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