System clock frequency supports up to 48MHz
Machine cycle maximum 1TSYS @ FSYS≤24MHz
Machine cycle maximum 2TSYS@ FSYS=48MHz
Program FLASH:64K×8Bit
Data FLASH:1K×8Bit
General RAM: 256×8Bit
Universal XRAM: 4K×8Bit
Program FLASH supports partition protection andIAP
Data FLASH supports partition protection
HSI-Internal high-speed oscillator: 48MHz
HSE-External high-speed oscillator: 8MHz/16MHz
LSE-External low-speed oscillator: 32.768KHz
LSI-Internal low-speed oscillator: 125KHz
Up to 46 GPIOs
Support pull-up/down resistor function
Support edge (rising edge/falling edge/both edge)interrupt
Support wake-up function
Support all external port interrupts
Up to 8 timer interrupts
Other peripheral interrupts
WDT/WWDT timer (watchdog/ window watchdogtimer)
Up to 5 timers: Timer0/1, Timer2, Timer3/4
LSE Timer (support sleep wake function)
WUT (wake-up timer)
BRT/ BRT1 (baud rate clock generation timer)
CRC16 (CRC16-CCITT)
Support 32bit/16bit, 16bit/16bit, 16bit×16bit
50% duty cycle, frequency can be set freely
6 channels enhanced PWM
6 independent cycle counters
Support independent /complementary/ synchronous/group mode
Support edge alignment/center alignment
Support complementary mode dead zone delayfunction
Support mask function and fault protectionfunction
1xSPI (communication rate up to 6Mb/s)
1xI2C (communication rate up to 400Kb/s)
Up to 4xUART (baud rate up to 1Mb/s)
2.1V~5.5V
-40℃~105℃
1.8V/2.0V/2.5V/3.5V
2.0V ~ 4.6V, 16 levels optional
Up to 23 AD external channels
Optional reference voltage (2.0V/2.4V/3.0V/VDD)
Can detect internal 1.2V reference voltage
Support hardware trigger start conversion function
Support a set of result digital comparison function
Optional duty cycle: 1/4, 1/5, 1/6, 1/8
Optional three clock sources: LSI/LSE/system clock
Traditional resistive LCD, optional BIAS: 1/2, 1/3, 1/4
Support work in sleep mode
Support fast charging mode
Support energy-saving mode, the total resistance of voltagedivider can be 60K/225K/900K
Support up to 4COM x 36SEG, 5COM x 35SEG6COM x 34SEG, 8COM x 32SEG
Optional duty cycle: 1/4, 1/5, 1/6, 1/8
Support two modes: common cathode/common anode
Optional three clock sources: LSI/LSE/system clock
Optional COM, SEG current
Support up to 4COM x 28SEG, 5COM x 27SEG6COM x 26SEG, 8COM x 24SEG
5 options for the positive terminal, internal - 1.2V/VDD divider for the negative terminal
Comparator supports unilateral/bilateral hysteresis
Optional hysteresis voltage 10/20/60mV
Support comparison output trigger EPWM brakeGPIO port
The internal 1.2V/VDD divider of the negativeterminal can be connected to the internal ADCchannel
Supports output latching
Idle mode 1/2
Sleep mode (STOP)
Each chip has an independent ID number
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