Product Features

• Compatible with MCS-51 1T Instruction System

  The system clock frequency supports up to 48MHz

  The fastest machine cycle supports 1TSYS @FSYS≤24MHz

  The fastest machine cycle supports 2TSYS @FSYS＝48MHz

• Memory

  Maximum program FLASH: 16K×8Bit

  Maximum Data FLASH: 1K×8Bit

  General RAM: 256×8Bit

  General XRAM: 1K×8Bit

  Program FLASH supports partition protection

• 4 Oscillation Modes

  HSI-Internal high-speed oscillator: 48MHz

  HSE-External high-speed oscillator: 8MHz/16MHz

  LSE-External low-speed oscillator: 32.768KHz

  LSI-Internal low-speed oscillator: 125KHz

• Low voltage reset function（LVR）

  1.8V/2.0V/2.5V/3.5V

• Low-voltage detection function（LVD）

  2.0V/2.2V/2.4V/2.7V/3.0V/3.7V/4.0V/4.3V

• GPIO

  Up to 22 GPIO

  All digital functions can be assigned to any GPIO

  Both support up/down resistance function

  Both support edge (rising edge/falling edge/doubleedge) interrup

  Support wake-up function

• Interrupt source

  Support all external port interrupts

  Up to 7 timer interrupts

  Other peripheral interrupts

• Timers

  WDT timer (watchdog timer)

  Up to 5 timers:

  Timer0/1, Timer2, Timer3/4

  LSE Timer (Support sleep wake function)

  WUT (Wake-up timer)

  BRT (serial port baud rate clock generator)

• Communication module

  1xSPI (communication rate up to 6Mb/s)

  1xI2C (communication rate up to 400Kb/s)

  Up to 2xUART (baud rate up to 1Mb/s)

• Low power mode

  Idle mode（IDLE）

  Sleep mode（STOP）

• Operating voltage range

  2.1V～5.5V

• Operating temperature range

  -40℃～105℃

• Buzzer driver

  50% duty cycle, frequency can be set freely

• Enhanced PWM

  6 channels enhanced PWM

  6 mutually independent cycle counters

  Support independent/complementary/synchronous/groupmode

  Support edge alignment/center alignment

  Support complementary mode dead zone delayfunction

  Support mask function and brake function

• High-precision 12-bit ADC

  All GPIOs (22I/Os) support AD channels

  Optional reference voltage(1.2V/2.0V/2.4V/3.0V/VDD)

  Can detect internal 1.2V reference voltage

  Support hardware trigger start conversionfunction

  Support a set of result digital comparisonfunction

• Two analog comparators (ACMP0/1)

  5 options for positive terminal, internal 1.2V/VDD voltage divider for negative terminal

  Comparator supports unilateral/bilateral hysteresis

  Hysteresis voltage optional 10/20/60mV

  Support comparison output to trigger EPWM brake

  The internal 1.2V/VDD divider of the negativeterminal can be connected to the internal ADC channel

• Two-way operational amplifier（OP0/1）

  Three terminals of each op amp are multiplexed with GPIO port

  The positive end supports internal 1.2V input

  Support two modes of op amp/comparator

  Op amp output can be connected to internalADC channel

  The output of the op amp can be connected tothe input of the internal analog comparator

  Support offset voltage software trimming

• Programmable gain amplifier（PGA）

  Support offset voltage software trimming

  With sample and hold circuit (used with ADC)

  Multi-stage gain optional (1/2/4/8/16/32/64/128times)

  Support single-ended/pseudo-differential input

  PGA output can be connected to the internalADC channel

  PGA output can be connected to internal analogcomparator input

• Support 96-bit Unique ID Number (UID)

  Each chip has an independent ID number

• Support Two-wire Serial Programming and Debugging