System clock frequency supports up to 48MHz
Machine cycle maximum 1TSYS @ FSYS≤24MHz
Machine cycle maximum 2TSYS@ FSYS=48MHz
Program FLASH:32K×8Bit
Data FLASH:1K×8Bit
IRAM:256×8Bit
XRAM:2K×8Bit
Support BOOT function area,1K/2K/4K optiona
Program FLASH supports partition protection
HSI-Internal high-speed oscillator: 48MHz
HSE-External high-speed oscillator: 8MHz/16MHz
LSE-External low-speed oscillator: 32.768KHz
LSI-Internal low-speed oscillator: 125KHz
Up to 30 GPIOs
Support pull-up/down resistor function
Support edge (rising edge/falling edge/both edge) interrupt
Support wake-up function
Support all external port interrupts
Up to 7 timer interrupts
Other peripheral interrupts
WDT(watchdog timer)
Timer0/1,Timer2,Timer3/4
LSE Timer(Support wake up)
WUT (wake-up timer)
BRT(baud rate clock generation timer)
CRC16(CRC16-CCITT)
Support 32bit/16bit, 16bit/16bit, 16bit×16bit
50% duty cycle, frequency can be set freely
6 channels enhanced PWM
6 independent cycle counters
Support independent /complementary/ synchronous/group mode
Support edge alignment/center alignment
Support complementary mode dead zone delayfunction
1xSPI(communication rate up to 6Mb/s)
1xI2C (communication rate up to 400Kb/s)
2xUART (baud rate up to 1Mb/s)
UART1 can be mapped to any GPIO
2.1V~5.5V
-40℃~105℃
1.8V/2.0V/2.5V/3.5V
2.0V ~ 4.6V, 16 levels optional
Up to 30 AD external channels
Optional reference voltage (1.2V/2.0V/2.4V/3.0V/VDD)
Can detect internal 1.2V reference voltage
Support hardware trigger start conversion function
Support a set of result digital comparison function
Optional duty cycle: 1/4, 1/5, 1/6, 1/8
Optional three clock sources: LSI/LSE/system clock
Traditional resistive LCD, optional BIAS: 1/2, 1/3, 1/4
Support work in sleep mode
Support fast charging mode
Support energy-saving mode, the total resistance of voltagedivider can be 60K/225K/900K
Support up to 4COM x 20SEG, 5COM x 19SEG, 6COM x 18SEG, 8COM x 16SEG
Optional duty cycle: 1/4, 1/5, 1/6, 1/8
Support two modes: common cathode/common anode
Optional three clock sources: LSI/LSE/system clock
Optional COM, SEG current
Support up to 4COM x 20SEG、5COM x 19SEG, 6COM x 18SEG、8COM x 16SEG
4 options for the positive terminal, internal 1.2V/VDD divider forthe negative terminal
Comparator supports unilateral/bilateral hysteresis
The internal 1.2V/VDD divider of the negative terminal can beconnected to the internal ADC channel l
Three terminals of each operational amplifier are multiplexed withGPIO port
The positive terminal supports internal 1.2V input
Support two modes of operational amplifier /comparator
The output of the operational amplifier can be connected to theinput of the internal analog comparator
Idle mode(IDLE)
Sleep mode (STOP)
Each chip has an independent ID number
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