The system clock frequency supports up to 48MHz
The maximum machine cycle supports 1TSYS@FSYS=16MHz
The maximum machine cycle supports 2TSYS @FSYS=24MHz
The maximum machine cycle supports 3TSYS @FSYS=48MHz
Maximum program FLASH: 64K×8Bit
Data FLASH:4K×8Bit
Maximum Data BOOT FLASH: 16K×8Bit
General RAM: 256×8Bit
Universal XRAM: 4K×8Bit
Program FLASH supports partition protection
HSI-Internal high-speed oscillator: 48MHz
HSE-External high-speed oscillator: 8MHz/16MHz
LSE-External low-speed oscillator: 32.768KHz
LSI-Internal low-speed oscillator: 125KHz
1.8V/2.0V/2.5V/3.5V
2.0V/2.2V/2.4V/2.7V/3.0V/3.7V/4.0V/4.3V
Up to 30 GPIO
All digital functions can be assigned to any GPIO
Both support pull-up/down resistor function
Both support edge (rising edge/ falling edge/ bothedge) interrupt
Support wake-up function
Support all external port interrupts
Up to 8 timer interrupts
Other peripheral interrupts
2.1V~5.5V
-40℃~105℃
Up to 1xSPI (communication rate up to 6Mb/s)
1xI2C (communication rate up to 400Kb/s)
Up to 2xUART (baud rate up to 1Mb/s)
Idle mode(IDLE)
Sleep mode(STOP)
WDT wake-up (watchdog timer)
Up to 5 timers: Timer0/1, Timer2, Timer3/4
LSE_Timer (Support sleep wake function)
50% duty cycle, frequency can be set freely
6 channels enhanced PWM
6 mutually independent cycle counters
Support independent/complementary/synchronous/groupmode
Support edge alignment/center alignment
Support complementary mode dead zone delayfunction
Support mask function and brake function
All GPIOs (30I/Os) support AD channels
Optional reference voltage (2.0V/2.4V/3.0V/VDD)
Can detect internal 1.2V reference voltage
Support hardware trigger start conversionfunction
Support hardware trigger start conversion function
Support a set of result digital comparison function
Each chip has an independent ID number
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